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1/25 MSM6404a/6404vs ? semiconductor general description the MSM6404a microcontroller is a low-power device implemented in complementary metal- oxide semiconductor technology. the MSM6404a is optimized for high-speed processing and complicated-control applications. the MSM6404vs is a cmos 4-bit microcontroller that employs an external eprom using a piggy-back package in place of the program memory (rom) internal to the MSM6404a. the MSM6404vs can be used for program development verification because the programs can be modified by programming an external eprom 2732 equivalent or 2764a equivalent. features ? mask rom (MSM6404a) : 4000 words 8 bits external rom (MSM6404vs) : 8196 words 8 bits ? ram (including the stack area) : 256 words 4 bits ? i/o port input-output port : 8 ports 4 bits input port : 1 port 4 bits 4 bits are for input ports having a latch; the other 32 bits are input/output ports that allow bit manipulation ? three built-in counters : 12-bit time-base counter 12-bit programmable timer 8-bit high-speed programmable timer/event counter ? built-in 8-bit serial i/o register (with 3-bit counter) ? five interrupts with five priority levels (4 internal, 1 external) ? 32 stacks (in ram) ? power-down features ? minimum instruction execution time : 952 ns @ 4.2 mhz clock ? instruction systems suitable for control ? fully static operation ? low power consumption ? single 5 v supply ? package options: MSM6404a 42-pin plastic dip (dip42-p-600-2.54) : (product name : MSM6404a- rs) 44-pin plastic qfp (qfp44-p-910-0.80-k) : (product name : MSM6404a- gs-k) 44-pin plastic qfp (qfp44-p-910-0.80-2k) : (product name : MSM6404a- gs-2k) MSM6404vs 42-pin ceramic piggyback (adip42-c-600-2.54) : (product name : MSM6404vs) indicates a code number. ? semiconductor MSM6404a/6404vs high speed and high performance 4-bit microcontroller e2e0013-38-93 this version: sep. 1998 previous version: mar. 1996
2/25 MSM6404a/6404vs ? semiconductor block diagram MSM6404a 3210 p8 3210 p7 3210 p6 3210 p5 3210 p4 3210 p3 3210 p2 3210 p1 3210 p0 ram 16 16 4 bits dec hl sp 12-bit timer 8-bit t/c p9 8-bit sr pa c alu acc instr dec f pc pb 0 dec rom 4000 8 bits timing & control interrupt control pc inte pd irq 12-bit tbc osc 0 osc 1 test reset v dd gnd int cin tmo tck sck , cto , clk si so 11
3/25 MSM6404a/6404vs ? semiconductor block diagram (continued) MSM6404vs 3210 p8 3210 p7 3210 p6 3210 p5 3210 p4 3210 p3 3210 p2 3210 p1 3210 p0 ram 16 16 4 bits dec hl sp 12-bit timer 8-bit t/c p9 8-bit sr pa c alu acc instr dec f pc pb 0 timing & control interrupt control pc inte pd irq 12-bit tbc osc 0 osc 1 test reset v dd gnd int cin tmo tck sck , cto , clk si so 12 rv dv i 0 to i 7 a 0 to a 12
4/25 MSM6404a/6404vs ? semiconductor pin configuration (top view) 20 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 p0.3 p4.0 p4.1 p4.2 p4.3 p3.0 p3.1 p3.2 p3.3 osc 0 osc 1 reset test p2.0 p2.1 p2.2 p2.3 p0.0 p0.1 p0.2 p1.1 v dd p5.3 p5.2 p5.1 p5.0 p6.3 p6.2 p6.1 p6.0 p7.3 p7.2 p7.1 p7.0 p8.3 p8.2 p8.1 p8.0 p1.3 p1.2 23 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 21 gnd p1.0 22 42-pin plastic dip
5/25 MSM6404a/6404vs ? semiconductor pin configuration (top view) (continued) nc: no-connection pin 44-pin plastic qfp 33 32 31 30 29 28 27 26 25 24 23 1 2 3 4 5 6 7 8 9 10 11 p3.1 p3.2 p3.3 osc 0 osc 1 reset test p2.0 p2.1 p2.2 p2.3 p6.2 p6.1 p6.0 nc p7.3 p7.2 p7.1 p7.0 p8.3 p8.2 p8.1 44 43 42 41 40 39 38 37 36 35 34 p3.0 p4.3 p4.2 p4.1 p4.0 v dd p5.3 p5.2 p5.1 p5.0 p6.3 12 13 14 15 16 17 18 19 20 21 22 p0.0 p0.1 p0.2 p0.3 gnd nc p1.0 p1.1 p1.2 p1.3 p8.0
6/25 MSM6404a/6404vs ? semiconductor 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 p4.0 p4.1 p4.2 p4.3 p3.0 p3.1 p3.2 p3.3 osc 0 osc 1 reset test p2.0/ int p2.1 p2.2 p2.3 p0.0 p0.1/ sck p0.2/so p0.3/si gnd v dd p5.3 p5.2 p5.1 p5.0 p6.3 p6.2 p6.1 p6.0 p7.3 p7.2 p7.1 p7.0 p8.3 p8.2 p8.1 p8.0 p1.3 p1.2/ tck p1.1/ tmo p1.0/ cin q v pp /v dd w a12 e a7 r a6 t a5 y a4 u a3 i a2 o a1 ! 0 a0 !1 i0 !2 i1 ! 3 i2 ! 4 gnd v dd @8 pgm /v dd @ 7 v dd @6 a8 @ 5 a9 @ 4 a11 @3 oe /gnd @2 a10 @1 ce /gnd @ 0 i6 ! 8 i5 ! 7 i4 !6 i3 !5 i7 !9 pin configuration (top view) (continued) 42-pin ceramic piggyback
7/25 MSM6404a/6404vs ? semiconductor pin descriptions symbol type description during reset p0.0 i/o "1" p0.1/ sck p0.2/so p0.3/si p1.0/ cin i/o p1.0 is shared with counter input ( cin ). "1" p1.1/ tmo p1.1 is shared with timer output ( tmo ). p1.2/ tck p1.3 p2.0/ int i p2.0 is shared with external interrupt input ( int ). the latch is reset. p2.1 input port with a latch, built-in pull-up resistor p2.2 p2.3 p3.0 to 3.3 "0" p4.0 to 4.3 p5.0 to 5.3 p6.0 to 6.3 p7.0 to 7.3 i/o "0" p8.0 to 8.3 osc 0 i oscillation waveform crystal connection pins for clock oscillation test o pulse output (test pin for manufacturer) reset i v dd power supply voltage pins gnd p0.1 is shared with serial clock ( sck ) input/output. p0.2 is shared with serial data (so) output. p0.3 is shared with serial data (si) input. p1.2 is shared with timer clock input ( tck ). i/o i/o i/o i/o "1" "0" "0" osc 1 input pin for system reset o 8-bit output ports (at opt instruction execution) i/o note: 1. the ports except for pins p2.0 to p2.3 are pseudo bidirectional ports. 2. when each port is used for output, the MSM6404a can drive one ttl (one input) and the MSM6404vs can drive one ls ttl (one input). upper pins for MSM6404vs symbol type description a0 to a12 i0 to i7 ce /gnd i oe /gnd i o i data input chip enable input output enable input address output i pgm /v dd program input v dd power supply voltage pins gnd v pp /v dd programed power supply voltage pin
8/25 MSM6404a/6404vs ? semiconductor absolute maximum ratings (MSM6404a) parameter symbol condition rating unit power supply voltage v dd ta = 25c C0.3 to +7 v input voltage v i C0.3 to v dd v output voltage v o C0.3 to v dd v power dissipation p d 200 max. mw ta = 25c per output 50 max. mw ta = 25c per package storage temperature t stg C55 to +150 c recommended operating conditions (MSM6404a) note: refer to the f osc -v dd characteristic in operating characteristics for the relation-ship between power supply voltage and operating frequency. parameter symbol condition range unit power supply voltage v dd f osc 1 mhz 3 to 6 v 4.5 to 5.5 v f osc 4.2 mhz data-hold voltage v ddh 2 to 6 v f osc = 0 hz operating temperature t op C40 to +85 c fan out n 15 mos load ttl load 1
9/25 MSM6404a/6404vs ? semiconductor electrical characteristics (MSM6404a) dc characteristics parameter symbol condition min. typ. max. unit "h" input voltage*1, *2 v ih 2.4 v dd v "h" input voltage*3, *4 v ih 3.6 v dd v "l" input voltage v il C0.3 +0.8 v "h" output voltage*1, *5 v oh i o = C15 m a 4.2 v v ol i o = 1.6 ma 0.4 v v ol i o = 15 m a 0.4 v input current*3 i ih /i il v i = v dd /0 v 15/C15 m a input current*2, *4 1/C30 "h" output current*1 i oh v o = 2.4 v C0.1 ma i oh v o = 0.4 v C1.2 ma input capacitance c i f = 1 mhz, ta = 25c 5 pf output capacitance c o 7 power supply current (in stop mode) i dds v dd = 2 v, no load, ta = 25c 0.2 5 m a no load 1 100 m a power supply current i dd crystal oscillation f = 4.194304 mhz, no load 612ma "l" output voltage*1 "l" output voltage*5 "h" output current*1 i ih /i il v i = v dd /0 v m a (v dd = 5 v 10%, ta = C40 to +85c) *1 applied to p0, p1, p3, p4, p5, p6, p7 and p8. *2 applied to p2. *3 applied to osc 0 . *4 applied to reset . *5 applied to osc 1 .
10/25 MSM6404a/6404vs ? semiconductor ac characteristics (MSM6404a) parameter symbol condition min. typ. max. unit clock (osc 0 ) pulse width t f w 119 ns cycle time t cy 952 ns input data setup time t ds 120 ns input data hold time t dh 120 ns sr/tm clock pulse width t ws /t wt 120 ns ct clock pulse width p2 input data clock pulse width t wp 120 ns (v dd = 5 v 10%, ta = C40 to +85c) sr data setup time t ss 120 ns sr data hold time t sh 120 ns data delay time t dr c l = 15 pf t cy + 300 ns data delay time at mode switching t dcr c l = 15 pf 7/8 t cy + 300 ns t di1 c l = 15 pf 6/8 t cy + 300 ns t wc 2/8 t cy + 120 ns data delay time at opt instruction ct/tm data delay time using tbc clock sr/tm data delay time using port clock ct data delay time using port clock ct data delay time using external clock sr/tm data delay time using external clock sr clock invalid time int invalid time t di2 c l = 15 pf 7/8 t cy + 300 ns t ct /t tt c l = 15 pf 2/8 t cy + 360 ns t sr /t tr c l = 15 pf t cy + 480 ns t cr c l = 15 pf 10/8 t cy + 480 ns t cp c l = 15 pf 2/8 t cy + 360 ns t sp /t tp c l = 15 pf 360 ns t sinh 2/8 t cy ns t iinh 1/8 t cy ns data delay time at opt instruction
11/25 MSM6404a/6404vs ? semiconductor timing diagrams (MSM6404a) output conditions 1mc t cy t dr t dcr t di1 t di2 t ct t tt t sr t tr t cr t cp t sp t tp osc 0 0, 1, 3 4, 5, 6 7 or 8 pa = p0, p1, p3 p4, p5, p6 p7, p8 pa = 9 or a p0.1 p0.2 p0.3 opt inst. p4 opt inst. p5 tbc clock p0.1 p1.1 ct tm p0.2 p0.1 clock* sr p1.1 p1.2 clock* tm p0.1 p1.0 clock* ct p0.1 ext clock p1.0 p1.2 ext clock p0.1 ct p0.2 sr p1.1 tm * output data to port is clock for sr, tm or ct.
12/25 MSM6404a/6404vs ? semiconductor input conditions t sinh 1mc t iinh t ss t sh input data t wc t ws t ds t dh input data t f w t f w 1mc osc 0 p0, p1, p2 p3, p4, p5 p6, p7, p8 p0.1 sr clock p1.2 tm clock p2 p1.0 ct clock p0.1 sr clock p0.3 si osc 0 t wt t wp t sinh : p0.1 (sr clock) inh period during lmsr inst. (note : p0.1 is used for clock of sr.) t iinh : p2.0 (interrupt) inh period during rpb and rpbd inst.
13/25 MSM6404a/6404vs ? semiconductor 0 12345678910 C0.1 C0.2 C0.3 C0.4 C0.5 C0.6 C0.7 C0.8 C0.9 C1.0 i oh (ma) v oh (v) 0 12345678910 2 4 6 8 10 12 14 16 18 20 i ol (ma) v ol (v) 0 12345678910 1 2 3 4 5 6 7 8 9 10 f osc (mhz) v dd (v) 0 C40 C20 0 20 40 60 80 100120 1 2 3 4 5 6 7 8 9 10 f osc (mhz) ta ( c ) 12345678910 v dd (v) 0 100 n 1 m 10 m 100 m 1 m 10 m i dd (a) 2 mhz f osc = 4 mhz 0 hz v dd = 5 v v dd = 5 v 6 v 4 v 3 v v dd = 6 v 5 v 4 v 3 v 100 khz ta = 25c ta = 25c cl = 15 pf ta = 25c, cl =1 5 pf ta = 25c, no load 500 khz 1 mhz operating characteristics (MSM6404a) current (i oh ) vs voltage (v oh ) for high state output current (i ol ) vs voltage (v ol ) for low state output maximum clock frequency (f osc ) vs temperature (ta) supply current (i dd ) vs supply voltage (v dd ) maximum clock frequency (f osc ) vs supply voltage (v dd )
14/25 MSM6404a/6404vs ? semiconductor absolute maximum ratings (MSM6404vs) recommended operating conditions (MSM6404vs) parameter symbol condition rating unit power supply voltage v dd ta = 25c C0.3 to +7 v input voltage v i C0.3 to v dd v output voltage v o C0.3 to v dd v power dissipation p d 200 max. mw ta = 25c per output 50 max. mw ta = 25c per package storage temperature t stg C55 to +150 c parameter symbol condition range unit power supply voltage v dd f osc 1 mhz 3 to 6 v 4.75 to 5.25 v f osc 4.2 mhz data-hold voltage v ddh 2 to 6 v f osc = 0 hz operating temperature t op 0 to +40 c fan out n 15 mos load lsttl load 1
15/25 MSM6404a/6404vs ? semiconductor electrical characteristics (MSM6404vs) dc characteristics parameter symbol condition min. typ. max. unit "h" input voltage*1, *2 v ih 3.6 v dd v "h" input voltage*3, *4 v ih 3.6 v dd v "l" input voltage v il C0.3 +0.8 v "h" output voltage*1, *5 v oh i o = C15 m a 4.2 v v ol i o = 0.4 ma 0.4 v v ol i o = 15 m a 0.4 v input current*3 i ih /i il v i = v dd /0 v 15/C15 m a input current*2, *4 1/C30 "h" output current*1 i oh v o = 2.4 v C0.1 ma i oh v o = 0.4 v C1.2 ma input capacitance c i f = 1 mhz, ta = 25c 5 pf output capacitance c o 7 power supply current*6 (in stop mode) i dds v dd = 2 v, no load, ta = 25c 1 5 m a no load 10 100 m a power supply current*6 i dd crystal oscillation f = 4.2 mhz, no load 612ma "l" output voltage*1 "l" output voltage*5 "h" output current*1 i ih /i il v i = v dd /0 v m a (v dd = 5 v 5%, ta = 0 to +40c) *1 applied to p0, p1, p3, p4, p5, p6, p7 and p8. *2 applied to p2. *3 applied to osc 0 . *4 applied to reset . *5 applied to osc 1 . *6 the eprom current is not included.
16/25 MSM6404a/6404vs ? semiconductor ac characteristics (MSM6404vs) parameter symbol condition min. typ. max. unit clock (osc 0 ) pulse width t f w 119 ns cycle time t cy 952 ns input data setup time t ds 120 ns input data hold time t dh 120 ns sr/tm clock pulse width t ws /t wt 120 ns ct clock pulse width p2 input data clock pulse width t wp 120 ns (v dd = 5 v 5%, ta = 0 to +40c) sr data setup time t ss 120 ns sr data hold time t sh 120 ns data delay time t dr c l = 15 pf t cy + 300 ns data delay time at mode switching t dcr c l = 15 pf 7/8 t cy + 300 ns t di1 c l = 15 pf 6/8 t cy + 300 ns t wc 2/8 t cy + 120 ns data delay time at opt instruction ct/tm data delay time using tbc clock sr/tm data delay time using port clock ct data delay time using port clock ct data delay time using external clock sr/tm data delay time using external clock sr clock invalid time int invalid time t di2 c l = 15 pf 7/8 t cy + 300 ns t ct /t tt c l = 15 pf 2/8 t cy + 360 ns t sr /t tr c l = 15 pf t cy + 480 ns t cr c l = 15 pf 10/8 t cy + 480 ns t cp c l = 15 pf 2/8 t cy + 360 ns t sp /t tp c l = 15 pf 360 ns t sinh 2/8 t cy ns t iinh 1/8 t cy ns data delay time at opt instruction
17/25 MSM6404a/6404vs ? semiconductor timing diagrams (MSM6404vs) output conditions t cy t dr t dcr t di1 t di2 t ct t tt t sr t tr t cr t cp t sp t tp osc 0 p0, p1, p3 p4, p5, p6 p7, p8 p0.1 p0.2 p1.1 opt inst. p4 opt inst. p5 tbc clock p0.1/ cto p1.1/ tmo p0.2/so p1.1/ tmo p0.1/ cto p1.0 clock p0.1 ext clock p1.0, p1.2 ext clock p0.1 clock p1.2 clock p0.1/ cto p0.2/so p1.1/ tmo 1mc 1mc t iinh osc 0 t sinh t sinh : p0.1/ sck inhibit period during lmsr inst. t iinh : p2.0/ int inhibit period during rpb and rpbd inst.
18/25 MSM6404a/6404vs ? semiconductor input conditions t ss t sh input data t wc t ws input data t f w t f w 1mc osc 0 p0, p1, p2 p3, p4, p5 p6, p7, p8 p0.1 sr clock p1.2 tm clock p2 p1.0 ct clock p0.1/ sck p0.3/si t wt t wp t ds t dh
19/25 MSM6404a/6404vs ? semiconductor operating characteristics (MSM6404vs) current (i oh ) vs voltage (v oh ) for high state output current (i ol ) vs voltage (v ol ) for low state output 0 12345678910 C0.1 C0.2 C0.3 C0.4 C0.5 C0.6 C0.7 C0.8 C0.9 C1.0 i oh (ma) v oh (v) 0 12345678910 2 4 6 8 10 12 14 16 18 20 i ol (ma) v ol (v) 12345678910 v dd (v) 0 100 n 1 m 10 m 100 m 1 m 10 m i dd (a) 2 mhz f osc = 4 mhz 0 hz v dd = 6 v 5 v 4 v 3 v v dd = 6 v 5 v 4 v 3 v 1 mhz 500 khz 100 khz ta = 25c, excluding pins a 0 -a 12 ta = 25c 0 12345678910 1 2 3 4 5 6 7 8 9 10 f osc (mhz) v dd (v) ta = 25c, c l = 15 pf ta = 25c, no load, excluding eprom current 0 C40 C20 0 20 40 60 80 100120 1 2 3 4 5 6 7 8 9 10 f osc (mhz) ta (c) v dd = 5 v, c l = 15 pf 500 n 5 m 50 m 500 m 5 m maximum clock frequency (f osc ) vs supply voltage (v dd ) supply current (i dd ) vs supply voltage (v dd ) maximum clock frequency (f osc ) vs temperature (ta)
20/25 MSM6404a/6404vs ? semiconductor functional description MSM6404vs interface to eprom eprom insertion method 2732 2764a 2732 eprom 2764a eprom eprom read timing t acc read data address 1mc t1 t2 t3 t4 t1 t f w t f w i 0 to i 7 a 0 to a 12 osc 0 ce , oe use eprom with t acc of less than 357 ns. read data is read into the instruction register in the first half of the t1 state.
21/25 MSM6404a/6404vs ? semiconductor differences between MSM6404a and MSM6404vs (piggyback) item MSM6404a MSM6404vs (piggyback) 1. ports p0, 1, 3 are set to "1" and ports p2, 4, 5, 6, 7, 8 are reset to "0" directly by the reset input signal. ports p0, 1, 3 are set to "1" and ports p2, 4, 5, 6, 7, 8 are initialized during reset cycle. after being reset, the timer continues to stop until data is set in it. it is undefined whether the timer starts or not after being reset. therefore, the timer should be initialized by software. serial out f/f (sof/f) is set to "0" after being reset. it is undefined whether serial out f/f (sof/f) is "0" or "1" after being reset. therefore the serial out f/f should be initialized by software. port initialization during reset 2. timer operation 3. shift register internal clock internal clock port input/output timing 4. input data are input at this time. input data are input at this time. internal clock synchronized with falling edge data are output at this time. data are output at this time. output ttl fo = "1" (i ol = 1.6 ma @ 0.4 v) lsttl fo = "1" (i ol = 0.4 ma @ 0.4 v) port input/output characteristics 5. p2.0-3 p2.0-3 v dd v dd v dd ttl compatible input cmos input p0.0-p8.3 p0.0-p8.3 (except p2.0-3) (except p2.0-3) up to 4 kbytes up to 8 kbytes accessible available rom capacity not available available ljp a 13 , lcal a 13 instruction internal clock output 6. 7.
22/25 MSM6404a/6404vs ? semiconductor (unit : mm) package dimensions dip42-p-600-2.54 package material lead frame material pin treatment solder plate thickness package weight (g) epoxy resin 42 alloy solder plating 5 m m or more 6.20 typ.
23/25 MSM6404a/6404vs ? semiconductor (unit : mm) notes for mounting the surface mount type package the sop, qfp, tsop, soj, qfj (plcc), shp and bga are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact okis responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). qfp44-p-910-0.80-k package material lead frame material pin treatment solder plate thickness package weight (g) epoxy resin 42 alloy solder plating 5 m m or more 0.35 typ. mirror finish
24/25 MSM6404a/6404vs ? semiconductor (unit : mm) notes for mounting the surface mount type package the sop, qfp, tsop, soj, qfj (plcc), shp and bga are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact okis responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). package material lead frame material pin treatment solder plate thickness package weight (g) epoxy resin 42 alloy solder plating 5 m m or more 0.41 typ. qfp44-p-910-0.80-2k mirror finish
25/25 MSM6404a/6404vs ? semiconductor (unit : mm) 42-pin ceramic piggyback adip42-c-600-2.54

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